久久精品国产精品亚洲精品_国内精品久久久久久久果冻传媒_黄网在线观看视频_xxxx日本少妇_91av在线免费观看视频_成人免费视频播放_人妻av中文系列_午夜欧美大尺度福利影院在线看_狠狠人妻久久久久久综合蜜桃_亚洲精品成人精品456_久久久欧美一区二区_亚洲怡红院在线

嵌入式OS--4G手機(jī)操作系統(tǒng)

嵌入式硬件設(shè)計(jì)

其他類(lèi)

　　Encounter RTL Compiler培訓(xùn)班

Course Description

In this course, you explore the features of the Cadence? Encounter? RTL Compiler with global synthesis technology. You learn several techniques to constrain designs, run static timing analysis, evaluate datapath logic, optimize for low power, and interface with other tools.

Learning Objectives

After completing this course, you will be able to:

• Apply the recommended global synthesis flow using Encounter RTL Compiler.
• Navigate the design database and manipulate design objects.
• Constrain designs for global synthesis and run static timing analysis.
• Optimize RTL designs for timing and area using several strategies.
• Diagnose and analyze synthesis results.
• Use the extended datapath features of the compiler.
• Analyze and synthesize the design for low-power.
• Interface with other tools and place-and-route flows.

Course Agenda

Note that this course can be tailored to better meet your needs –?contact the Cadence training staff?for specifics.

Unit 1

• About this Course
• Introduction to Encounter RTL Compiler
• HDL Modeling
• Synthesis Flow
• Datapath Synthesis
• Optimization Strategies

Unit 2

• Low-Power Synthesis
• Interface to Other Tools
• Test Synthesis